/*
 * Copyright (C) 2017-2018, NVIDIA CORPORATION. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
 * GNU General Public License for more details.
 *
 */

#ifndef __MACH_TEGRA_MC_REGS_T19X_H__
#define __MACH_TEGRA_MC_REGS_T19X_H__

/* Auto generated. Do not edit. */

#define MC_AONPC_PTSA_MAX_0	0x77c
#define MC_AONPC_PTSA_MAX_0_PTSA_MAX_AONPC_DEFAULT_MASK	0x7ff
#define MC_AONPC_PTSA_MIN_0	0x778
#define MC_AONPC_PTSA_MIN_0_PTSA_MIN_AONPC_DEFAULT_MASK	0x7ff
#define MC_AONPC_PTSA_RATE_0	0x774
#define MC_AONPC_PTSA_RATE_0_PTSA_RATE_AONPC_DEFAULT_MASK	0xfff
#define MC_APB_PTSA_MAX_0	0x4f0
#define MC_APB_PTSA_MAX_0_PTSA_MAX_APB_DEFAULT_MASK	0x7ff
#define MC_APB_PTSA_MIN_0	0x4ec
#define MC_APB_PTSA_MIN_0_PTSA_MIN_APB_DEFAULT_MASK	0x7ff
#define MC_APB_PTSA_RATE_0	0x4e8
#define MC_APB_PTSA_RATE_0_PTSA_RATE_APB_DEFAULT_MASK	0xfff
#define MC_AUD_PTSA_MAX_0	0x550
#define MC_AUD_PTSA_MAX_0_PTSA_MAX_AUD_DEFAULT_MASK	0x7ff
#define MC_AUD_PTSA_MIN_0	0x54c
#define MC_AUD_PTSA_MIN_0_PTSA_MIN_AUD_DEFAULT_MASK	0x7ff
#define MC_AUD_PTSA_RATE_0	0x548
#define MC_AUD_PTSA_RATE_0_PTSA_RATE_AUD_DEFAULT_MASK	0xfff
#define MC_BPMPPC_PTSA_MAX_0	0x764
#define MC_BPMPPC_PTSA_MAX_0_PTSA_MAX_BPMPPC_DEFAULT_MASK	0x7ff
#define MC_BPMPPC_PTSA_MIN_0	0x760
#define MC_BPMPPC_PTSA_MIN_0_PTSA_MIN_BPMPPC_DEFAULT_MASK	0x7ff
#define MC_BPMPPC_PTSA_RATE_0	0x75c
#define MC_BPMPPC_PTSA_RATE_0_PTSA_RATE_BPMPPC_DEFAULT_MASK	0xfff
#define MC_CIFLL_ISO_PTSA_MAX_0	0x1120
#define MC_CIFLL_ISO_PTSA_MAX_0_PTSA_MAX_CIFLL_ISO_DEFAULT_MASK	0x7ff
#define MC_CIFLL_ISO_PTSA_MIN_0	0x111c
#define MC_CIFLL_ISO_PTSA_MIN_0_PTSA_MIN_CIFLL_ISO_DEFAULT_MASK	0x7ff
#define MC_CIFLL_ISO_PTSA_RATE_0	0x1124
#define MC_CIFLL_ISO_PTSA_RATE_0_PTSA_RATE_CIFLL_ISO_DEFAULT_MASK	0xfff
#define MC_CIFLL_NISO_PTSA_MAX_0	0x1108
#define MC_CIFLL_NISO_PTSA_MAX_0_PTSA_MAX_CIFLL_NISO_DEFAULT_MASK	0x7ff
#define MC_CIFLL_NISO_PTSA_MIN_0	0x1104
#define MC_CIFLL_NISO_PTSA_MIN_0_PTSA_MIN_CIFLL_NISO_DEFAULT_MASK	0x7ff
#define MC_CIFLL_NISO_PTSA_RATE_0	0x110c
#define MC_CIFLL_NISO_PTSA_RATE_0_PTSA_RATE_CIFLL_NISO_DEFAULT_MASK	0xfff
#define MC_CIFLL_NVLRHP_LATENCY_ALLOWANCE_0	0x189c
#define MC_CIFLL_RING0X_PTSA_MAX_0	0x112c
#define MC_CIFLL_RING0X_PTSA_MAX_0_PTSA_MAX_CIFLL_RING0X_DEFAULT_MASK	0x7ff
#define MC_CIFLL_RING0X_PTSA_MIN_0	0x1128
#define MC_CIFLL_RING0X_PTSA_MIN_0_PTSA_MIN_CIFLL_RING0X_DEFAULT_MASK	0x7ff
#define MC_CIFLL_RING0X_PTSA_RATE_0	0x1130
#define MC_CIFLL_RING0X_PTSA_RATE_0_PTSA_RATE_CIFLL_RING0X_DEFAULT_MASK 0xfff
#define MC_CIFLL_SISO_PTSA_MAX_0	0x1114
#define MC_CIFLL_SISO_PTSA_MAX_0_PTSA_MAX_CIFLL_SISO_DEFAULT_MASK	0x7ff
#define MC_CIFLL_SISO_PTSA_MIN_0	0x1110
#define MC_CIFLL_SISO_PTSA_MIN_0_PTSA_MIN_CIFLL_SISO_DEFAULT_MASK	0x7ff
#define MC_CIFLL_SISO_PTSA_RATE_0	0x1118
#define MC_CIFLL_SISO_PTSA_RATE_0_PTSA_RATE_CIFLL_SISO_DEFAULT_MASK	0xfff
#define MC_CLIENT_ORDER_ID_0_0	0x2a00
#define MC_CLIENT_ORDER_ID_10_0	0x2a28
#define MC_CLIENT_ORDER_ID_12_0	0x2a30
#define MC_CLIENT_ORDER_ID_13_0	0x2a34
#define MC_CLIENT_ORDER_ID_14_0	0x2a38
#define MC_CLIENT_ORDER_ID_15_0	0x2a3c
#define MC_CLIENT_ORDER_ID_16_0	0x2a40
#define MC_CLIENT_ORDER_ID_17_0	0x2a44
#define MC_CLIENT_ORDER_ID_18_0	0x2a48
#define MC_CLIENT_ORDER_ID_19_0	0x2a4c
#define MC_CLIENT_ORDER_ID_20_0	0x2a50
#define MC_CLIENT_ORDER_ID_21_0	0x2a54
#define MC_CLIENT_ORDER_ID_22_0	0x2a58
#define MC_CLIENT_ORDER_ID_23_0	0x2a5c
#define MC_CLIENT_ORDER_ID_24_0	0x2a60
#define MC_CLIENT_ORDER_ID_25_0	0x2a64
#define MC_CLIENT_ORDER_ID_26_0	0x2a68
#define MC_CLIENT_ORDER_ID_27_0	0x2a6c
#define MC_CLIENT_ORDER_ID_27_0_PCIE0W_ORDER_ID_ORDER_ID2	2
#define MC_CLIENT_ORDER_ID_27_0_PCIE0W_ORDER_ID_RANGE	5:4
#define MC_CLIENT_ORDER_ID_27_0_PCIE1W_ORDER_ID_RANGE	13:12
#define MC_CLIENT_ORDER_ID_27_0_PCIE2AW_ORDER_ID_RANGE	21:20
#define MC_CLIENT_ORDER_ID_27_0_PCIE3W_ORDER_ID_RANGE	29:28
#define MC_CLIENT_ORDER_ID_28_0	0x2a70
#define MC_CLIENT_ORDER_ID_28_0_PCIE4W_ORDER_ID_ORDER_ID3	3
#define MC_CLIENT_ORDER_ID_28_0_PCIE4W_ORDER_ID_RANGE	5:4
#define MC_CLIENT_ORDER_ID_28_0_PCIE5W_ORDER_ID_ORDER_ID1	1
#define MC_CLIENT_ORDER_ID_28_0_PCIE5W_ORDER_ID_RANGE	13:12
#define MC_CLIENT_ORDER_ID_29_0	0x2a74
#define MC_CLIENT_ORDER_ID_2_0	0x2a08
#define MC_CLIENT_ORDER_ID_30_0	0x2d00
#define MC_CLIENT_ORDER_ID_31_0	0x2d04
#define MC_CLIENT_ORDER_ID_3_0	0x2a0c
#define MC_CLIENT_ORDER_ID_4_0	0x2a10
#define MC_CLIENT_ORDER_ID_5_0	0x2a14
#define MC_CLIENT_ORDER_ID_6_0	0x2a18
#define MC_CLIENT_ORDER_ID_7_0	0x2a1c
#define MC_CLIENT_ORDER_ID_8_0	0x2a20
#define MC_CLIENT_ORDER_ID_9_0	0x2a24
#define MC_CLIENT_ORDER_ID_9_0_XUSB_HOSTW_ORDER_ID_ORDER_ID3	3
#define MC_CLIENT_ORDER_ID_9_0_XUSB_HOSTW_ORDER_ID_RANGE	13:12
#define MC_CONFIG_TSA_SINGLE_ARB_ENABLE_0	0xfe8
#define MC_CONFIG_TSA_SINGLE_ARB_ENABLE_0_SINGLE_ARB_ENABLE_ENABLE	1
#define MC_CONFIG_TSA_SINGLE_ARB_ENABLE_0_SINGLE_ARB_ENABLE_RANGE	0:0
#define MC_DIS_PTSA_MAX_0	0x424
#define MC_DIS_PTSA_MAX_0_PTSA_MAX_DIS_DEFAULT_MASK	0x7ff
#define MC_DIS_PTSA_MIN_0	0x420
#define MC_DIS_PTSA_MIN_0_PTSA_MIN_DIS_DEFAULT_MASK	0x7ff
#define MC_DIS_PTSA_RATE_0	0x41c
#define MC_DIS_PTSA_RATE_0_PTSA_RATE_DIS_DEFAULT_MASK	0xfff
#define MC_DLA0FALPC_PTSA_MAX_0	0x3174
#define MC_DLA0FALPC_PTSA_MAX_0_PTSA_MAX_DLA0FALPC_DEFAULT_MASK	0x7ff
#define MC_DLA0FALPC_PTSA_MIN_0	0x3170
#define MC_DLA0FALPC_PTSA_MIN_0_PTSA_MIN_DLA0FALPC_DEFAULT_MASK	0x7ff
#define MC_DLA0FALPC_PTSA_RATE_0	0x316c
#define MC_DLA0FALPC_PTSA_RATE_0_PTSA_RATE_DLA0FALPC_DEFAULT_MASK	0xfff
#define MC_DLA0XA2_PTSA_MAX_0	0x3938
#define MC_DLA0XA2_PTSA_MAX_0_PTSA_MAX_DLA0XA2_DEFAULT_MASK	0x7ff
#define MC_DLA0XA2_PTSA_MIN_0	0x3934
#define MC_DLA0XA2_PTSA_MIN_0_PTSA_MIN_DLA0XA2_DEFAULT_MASK	0x7ff
#define MC_DLA0XA2_PTSA_RATE_0	0x3930
#define MC_DLA0XA2_PTSA_RATE_0_PTSA_RATE_DLA0XA2_DEFAULT_MASK	0xfff
#define MC_DLA0XA3_PTSA_MAX_0	0x3368
#define MC_DLA0XA3_PTSA_MAX_0_PTSA_MAX_DLA0XA3_DEFAULT_MASK	0x7ff
#define MC_DLA0XA3_PTSA_MIN_0	0x3364
#define MC_DLA0XA3_PTSA_MIN_0_PTSA_MIN_DLA0XA3_DEFAULT_MASK	0x7ff
#define MC_DLA0XA3_PTSA_RATE_0	0x3360
#define MC_DLA0XA3_PTSA_RATE_0_PTSA_RATE_DLA0XA3_DEFAULT_MASK	0xfff
#define MC_DLA0XA_PTSA_MAX_0	0x7e8
#define MC_DLA0XA_PTSA_MAX_0_PTSA_MAX_DLA0XA_DEFAULT_MASK	0x7ff
#define MC_DLA0XA_PTSA_MIN_0	0x7e4
#define MC_DLA0XA_PTSA_MIN_0_PTSA_MIN_DLA0XA_DEFAULT_MASK	0x7ff
#define MC_DLA0XA_PTSA_RATE_0	0x7e0
#define MC_DLA0XA_PTSA_RATE_0_PTSA_RATE_DLA0XA_DEFAULT_MASK	0xfff
#define MC_DLA1FALPC_PTSA_MAX_0	0x3308
#define MC_DLA1FALPC_PTSA_MAX_0_PTSA_MAX_DLA1FALPC_DEFAULT_MASK	0x7ff
#define MC_DLA1FALPC_PTSA_MIN_0	0x3304
#define MC_DLA1FALPC_PTSA_MIN_0_PTSA_MIN_DLA1FALPC_DEFAULT_MASK	0x7ff
#define MC_DLA1FALPC_PTSA_RATE_0	0x3300
#define MC_DLA1FALPC_PTSA_RATE_0_PTSA_RATE_DLA1FALPC_DEFAULT_MASK	0xfff
#define MC_DLA1XA2_PTSA_MAX_0	0x3944
#define MC_DLA1XA2_PTSA_MAX_0_PTSA_MAX_DLA1XA2_DEFAULT_MASK	0x7ff
#define MC_DLA1XA2_PTSA_MIN_0	0x3940
#define MC_DLA1XA2_PTSA_MIN_0_PTSA_MIN_DLA1XA2_DEFAULT_MASK	0x7ff
#define MC_DLA1XA2_PTSA_RATE_0	0x393c
#define MC_DLA1XA2_PTSA_RATE_0_PTSA_RATE_DLA1XA2_DEFAULT_MASK	0xfff
#define MC_DLA1XA3_PTSA_MAX_0	0x3374
#define MC_DLA1XA3_PTSA_MAX_0_PTSA_MAX_DLA1XA3_DEFAULT_MASK	0x7ff
#define MC_DLA1XA3_PTSA_MIN_0	0x3370
#define MC_DLA1XA3_PTSA_MIN_0_PTSA_MIN_DLA1XA3_DEFAULT_MASK	0x7ff
#define MC_DLA1XA3_PTSA_RATE_0	0x336c
#define MC_DLA1XA3_PTSA_RATE_0_PTSA_RATE_DLA1XA3_DEFAULT_MASK	0xfff
#define MC_DLA1XA_PTSA_MAX_0	0x7f4
#define MC_DLA1XA_PTSA_MAX_0_PTSA_MAX_DLA1XA_DEFAULT_MASK	0x7ff
#define MC_DLA1XA_PTSA_MIN_0	0x7f0
#define MC_DLA1XA_PTSA_MIN_0_PTSA_MIN_DLA1XA_DEFAULT_MASK	0x7ff
#define MC_DLA1XA_PTSA_RATE_0	0x7ec
#define MC_DLA1XA_PTSA_RATE_0_PTSA_RATE_DLA1XA_DEFAULT_MASK	0xfff
#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE_0	0xdf8
#define MC_EMEM_ARB_MISC2_0	0xc8
#define MC_EMEM_ARB_MISC2_0_BACKING_RD_ON_ALL_64BYTE_WR_ENABLE	1
#define MC_EMEM_ARB_MISC2_0_BACKING_RD_ON_ALL_64BYTE_WR_RANGE	2:2
#define MC_EMEM_ARB_MISC2_0_DL_ONLY_ARB_ENABLE	1
#define MC_EMEM_ARB_MISC2_0_DL_ONLY_ARB_RANGE	31:31
#define MC_EMEM_ARB_MISC2_0_SYNC_MON_DISABLE	0
#define MC_EMEM_ARB_MISC2_0_SYNC_MON_ENABLE	1
#define MC_EMEM_ARB_MISC2_0_SYNC_MON_RANGE	30:30
#define MC_EMEM_ARB_MISC3_0	0x23c
#define MC_EMEM_ARB_MISC3_0_BC2AA_HOLDOFF_MAX_THRESHOLD_R_RANGE	6:0
#define MC_EMEM_ARB_MISC3_0_BC2AA_HOLDOFF_MAX_THRESHOLD_W_RANGE	14:8
#define MC_EMEM_ARB_MISC3_0_BC2AA_HOLDOFF_MIN_THRESHOLD_R_RANGE	19:16
#define MC_EMEM_ARB_MISC3_0_BC2AA_HOLDOFF_MIN_THRESHOLD_W_RANGE	23:20
#define MC_EMEM_ARB_OVERRIDE_0	0xe8
#define MC_EMEM_ARB_OVERRIDE_0_TS2AA_HOLDOFF_OVERRIDE_DISABLE	0
#define MC_EMEM_ARB_OVERRIDE_0_TS2AA_HOLDOFF_OVERRIDE_ENABLE	1
#define MC_EMEM_ARB_OVERRIDE_0_TS2AA_HOLDOFF_OVERRIDE_RANGE	8:8
#define MC_EMEM_ARB_REFPB_HP_CTRL_0	0x6f0
#define MC_EMEM_ARB_REFPB_HP_CTRL_0_REFPB_THRESH_DISABLE_HP_RANGE	14:8
#define MC_EMEM_ARB_REFPB_HP_CTRL_0_REFPB_THRESH_ENABLE_HP_RANGE	6:0
#define MC_EQOSPC_PTSA_MAX_0	0x758
#define MC_EQOSPC_PTSA_MAX_0_PTSA_MAX_EQOSPC_DEFAULT_MASK	0x7ff
#define MC_EQOSPC_PTSA_MIN_0	0x754
#define MC_EQOSPC_PTSA_MIN_0_PTSA_MIN_EQOSPC_DEFAULT_MASK	0x7ff
#define MC_EQOSPC_PTSA_RATE_0	0x750
#define MC_EQOSPC_PTSA_RATE_0_PTSA_RATE_EQOSPC_DEFAULT_MASK	0xfff
#define MC_FREE_BANK_QUEUES_0	0xea4
#define MC_FREE_BANK_QUEUES_0_HP_CPU_THROTTLE_EN_DISABLE	0
#define MC_FREE_BANK_QUEUES_0_HP_CPU_THROTTLE_EN_ENABLE	1
#define MC_FREE_BANK_QUEUES_0_HP_CPU_THROTTLE_EN_RANGE	16:16
#define MC_FTOP_PTSA_RATE_0_PTSA_RATE_FTOP_DEFAULT_MASK	0xfff
#define MC_HDAPC_PTSA_MAX_0	0x630
#define MC_HDAPC_PTSA_MAX_0_PTSA_MAX_HDAPC_DEFAULT_MASK	0x7ff
#define MC_HDAPC_PTSA_MIN_0	0x62c
#define MC_HDAPC_PTSA_MIN_0_PTSA_MIN_HDAPC_DEFAULT_MASK	0x7ff
#define MC_HDAPC_PTSA_RATE_0	0x628
#define MC_HDAPC_PTSA_RATE_0_PTSA_RATE_HDAPC_DEFAULT_MASK	0xfff
#define MC_HOST_PTSA_MAX_0	0x520
#define MC_HOST_PTSA_MAX_0_PTSA_MAX_HOST_DEFAULT_MASK	0x7ff
#define MC_HOST_PTSA_MIN_0	0x51c
#define MC_HOST_PTSA_MIN_0_PTSA_MIN_HOST_DEFAULT_MASK	0x7ff
#define MC_HOST_PTSA_RATE_0	0x518
#define MC_HOST_PTSA_RATE_0_PTSA_RATE_HOST_DEFAULT_MASK	0xfff
#define MC_HUB2MCF_REQ_DDA_ENABLE_0	0xfc0
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUBINT_DDA_ENABLE_DISABLED	0
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUBINT_DDA_ENABLE_ENABLED	1
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUBINT_DDA_ENABLE_RANGE	2:2
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUBORD_DDA_ENABLE_DISABLED	0
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUBORD_DDA_ENABLE_ENABLED	1
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUBORD_DDA_ENABLE_RANGE	1:1
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUB_DDA_ENABLE_DISABLED	0
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUB_DDA_ENABLE_ENABLED	1
#define MC_HUB2MCF_REQ_DDA_ENABLE_0_HUB_DDA_ENABLE_RANGE	0:0
#define MC_HUBINT_HUB2MCF_REQ_DDA_MAX_0	0xfbc
#define MC_HUBINT_HUB2MCF_REQ_DDA_MAX_0_HUBINT_DDA_MAX_DEFAULT_MASK	0x7ff
#define MC_HUBINT_HUB2MCF_REQ_DDA_RATE_0	0xfb0
#define MC_HUBINT_HUB2MCF_REQ_DDA_RATE_0_HUBINT_DDA_RATE_DEFAULT_MASK	0xfff
#define MC_HUBORD_HUB2MCF_REQ_DDA_MAX_0	0xfb8
#define MC_HUBORD_HUB2MCF_REQ_DDA_MAX_0_HUBORD_DDA_MAX_DEFAULT_MASK	0x7ff
#define MC_HUBORD_HUB2MCF_REQ_DDA_RATE_0	0xfac
#define MC_HUBORD_HUB2MCF_REQ_DDA_RATE_0_HUBORD_DDA_RATE_DEFAULT_MASK	0xfff
#define MC_HUB_HUB2MCF_REQ_DDA_MAX_0	0xfb4
#define MC_HUB_HUB2MCF_REQ_DDA_MAX_0_HUB_DDA_MAX_DEFAULT_MASK	0x7ff
#define MC_HUB_HUB2MCF_REQ_DDA_RATE_0	0xfa8
#define MC_HUB_HUB2MCF_REQ_DDA_RATE_0_HUB_DDA_RATE_DEFAULT_MASK	0xfff
#define MC_HUB_VC_ARB_SEL_0	0x2954
#define MC_HUB_VC_ARB_SEL_0_ISO_WT_RANGE	6:2
#define MC_HUB_VC_ARB_SEL_0_NISO_WT_RANGE	16:12
#define MC_HUB_VC_ARB_SEL_0_SISO_WT_RANGE	11:7
#define MC_HUB_VC_ARB_SEL_0_VC_ARB_TYPE_RANGE	1:0
#define MC_ISP2PC_PTSA_MAX_0	0x4b08
#define MC_ISP2PC_PTSA_MAX_0_PTSA_MAX_ISP2PC_DEFAULT_MASK	0x7ff
#define MC_ISP2PC_PTSA_MIN_0	0x4b04
#define MC_ISP2PC_PTSA_MIN_0_PTSA_MIN_ISP2PC_DEFAULT_MASK	0x7ff
#define MC_ISP2PC_PTSA_RATE_0	0x4b00
#define MC_ISP2PC_PTSA_RATE_0_PTSA_RATE_ISP2PC_DEFAULT_MASK	0xfff
#define MC_ISPPC_PTSA_MAX_0	0x3a74
#define MC_ISPPC_PTSA_MAX_0_PTSA_MAX_ISPPC_DEFAULT_MASK	0x7ff
#define MC_ISPPC_PTSA_MIN_0	0x3a70
#define MC_ISPPC_PTSA_MIN_0_PTSA_MIN_ISPPC_DEFAULT_MASK	0x7ff
#define MC_ISPPC_PTSA_RATE_0	0x3a6c
#define MC_ISPPC_PTSA_RATE_0_PTSA_RATE_ISPPC_DEFAULT_MASK	0xfff
#define MC_ISP_PTSA_MAX_0	0x4a8
#define MC_ISP_PTSA_MAX_0_PTSA_MAX_ISP_DEFAULT_MASK	0x7ff
#define MC_ISP_PTSA_MIN_0	0x4a4
#define MC_ISP_PTSA_MIN_0_PTSA_MIN_ISP_DEFAULT_MASK	0x7ff
#define MC_ISP_PTSA_RATE_0	0x4a0
#define MC_ISP_PTSA_RATE_0_PTSA_RATE_ISP_DEFAULT_MASK	0xfff
#define MC_JPG_PTSA_MAX_0	0x58c
#define MC_JPG_PTSA_MAX_0_PTSA_MAX_JPG_DEFAULT_MASK	0x7ff
#define MC_JPG_PTSA_MIN_0	0x588
#define MC_JPG_PTSA_MIN_0_PTSA_MIN_JPG_DEFAULT_MASK	0x7ff
#define MC_JPG_PTSA_RATE_0	0x584
#define MC_JPG_PTSA_RATE_0_PTSA_RATE_JPG_DEFAULT_MASK	0xfff
#define MC_LATENCY_ALLOWANCE_AONDMA_0_0	0x718
#define MC_LATENCY_ALLOWANCE_AON_0_0	0x714
#define MC_LATENCY_ALLOWANCE_APEDMA_0_0	0x724
#define MC_LATENCY_ALLOWANCE_APE_0_0	0x3dc
#define MC_LATENCY_ALLOWANCE_AXIAP_0_0	0x3a0
#define MC_LATENCY_ALLOWANCE_AXIS_0_0	0x3f8
#define MC_LATENCY_ALLOWANCE_BPMPDMA_0_0	0x710
#define MC_LATENCY_ALLOWANCE_BPMP_0_0	0x70c
#define MC_LATENCY_ALLOWANCE_CIFLL_WR_0_0	0x1100
#define MC_LATENCY_ALLOWANCE_DLA0_0_0	0x1020
#define MC_LATENCY_ALLOWANCE_DLA0_1_0	0x1024
#define MC_LATENCY_ALLOWANCE_DLA0_2_0	0x1a18
#define MC_LATENCY_ALLOWANCE_DLA1_0_0	0x1028
#define MC_LATENCY_ALLOWANCE_DLA1_1_0	0x102c
#define MC_LATENCY_ALLOWANCE_EQOS_0_0	0x700
#define MC_LATENCY_ALLOWANCE_ETR_0_0	0x3ec
#define MC_LATENCY_ALLOWANCE_HC_0_0	0x310
#define MC_LATENCY_ALLOWANCE_HDA_0_0	0x318
#define MC_LATENCY_ALLOWANCE_ISP2_0_0	0x370
#define MC_LATENCY_ALLOWANCE_ISP2_1_0	0x374
#define MC_LATENCY_ALLOWANCE_ISP3_0_0	0x1a14
#define MC_LATENCY_ALLOWANCE_MIU0_0_0	0x1054
#define MC_LATENCY_ALLOWANCE_MIU1_0_0	0x1058
#define MC_LATENCY_ALLOWANCE_MIU2_0_0	0x105c
#define MC_LATENCY_ALLOWANCE_MIU3_0_0	0x1060
#define MC_LATENCY_ALLOWANCE_MIU4_0_0	0x1a34
#define MC_LATENCY_ALLOWANCE_MIU5_0_0	0x1a38
#define MC_LATENCY_ALLOWANCE_MIU6_0_0	0x1a3c
#define MC_LATENCY_ALLOWANCE_MIU7_0_0	0x1a40
#define MC_LATENCY_ALLOWANCE_MPCORE_0_0	0x320
#define MC_LATENCY_ALLOWANCE_NVDEC_0_0	0x3d8
#define MC_LATENCY_ALLOWANCE_NVDEC_1_0	0x72c
#define MC_LATENCY_ALLOWANCE_NVDEC_2_0	0x1a30
#define MC_LATENCY_ALLOWANCE_NVDISPLAY_0_0	0x708
#define MC_LATENCY_ALLOWANCE_NVENC_0_0	0x328
#define MC_LATENCY_ALLOWANCE_NVENC_1_0	0x1050
#define MC_LATENCY_ALLOWANCE_NVENC_2_0	0x1a28
#define MC_LATENCY_ALLOWANCE_NVJPG_0_0	0x3e4
#define MC_LATENCY_ALLOWANCE_PCIE0_0_0	0x1064
#define MC_LATENCY_ALLOWANCE_PCIE1_0_0	0x1a00
#define MC_LATENCY_ALLOWANCE_PCIE2_0_0	0x1a04
#define MC_LATENCY_ALLOWANCE_PCIE3_0_0	0x1a08
#define MC_LATENCY_ALLOWANCE_PCIE4_0_0	0x1a0c
#define MC_LATENCY_ALLOWANCE_PCIE5_0_0	0x1a10
#define MC_LATENCY_ALLOWANCE_PCIE5_1_0	0x1a24
#define MC_LATENCY_ALLOWANCE_PVA0_0_0	0x1030
#define MC_LATENCY_ALLOWANCE_PVA0_1_0	0x1034
#define MC_LATENCY_ALLOWANCE_PVA0_2_0	0x1038
#define MC_LATENCY_ALLOWANCE_PVA0_3_0	0x1a1c
#define MC_LATENCY_ALLOWANCE_PVA1_0_0	0x103c
#define MC_LATENCY_ALLOWANCE_PVA1_1_0	0x1040
#define MC_LATENCY_ALLOWANCE_PVA1_2_0	0x1044
#define MC_LATENCY_ALLOWANCE_PVA1_3_0	0x1a20
#define MC_LATENCY_ALLOWANCE_RCEDMA_0_0	0x104c
#define MC_LATENCY_ALLOWANCE_RCE_0_0	0x1048
#define MC_LATENCY_ALLOWANCE_ROC_DMA_R_0_0	0xeac
#define MC_LATENCY_ALLOWANCE_SATA_0_0	0x350
#define MC_LATENCY_ALLOWANCE_SCEDMA_0_0	0x720
#define MC_LATENCY_ALLOWANCE_SCE_0_0	0x71c
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0_0	0x3c4
#define MC_LATENCY_ALLOWANCE_SDMMCA_0_0	0x3b8
#define MC_LATENCY_ALLOWANCE_SDMMC_0_0	0x3c0
#define MC_LATENCY_ALLOWANCE_SE_0_0	0x3e0
#define MC_LATENCY_ALLOWANCE_TSECB_0_0	0x3f0
#define MC_LATENCY_ALLOWANCE_TSEC_0_0	0x390
#define MC_LATENCY_ALLOWANCE_UFSHC_0_0	0x704
#define MC_LATENCY_ALLOWANCE_VI2_0_0	0x398
#define MC_LATENCY_ALLOWANCE_VIC_0_0	0x394
#define MC_LATENCY_ALLOWANCE_VIC_1_0	0x728
#define MC_LATENCY_ALLOWANCE_VIFAL_0_0	0x101c
#define MC_LATENCY_ALLOWANCE_WCAM_0	0xe5c
#define MC_LATENCY_ALLOWANCE_XUSB_0_0	0x37c
#define MC_LATENCY_ALLOWANCE_XUSB_1_0	0x380
#define MC_MC_SMMU_ISO_TBU_CCHK_REQ_PRI_CTRL_0	0x2968
#define MC_MC_SMMU_ISO_TBU_CCHK_REQ_PRI_CTRL_0_ISO_TBU_CCHK_EN_CTRL_RANGE	9:8
#define MC_MC_SMMU_PTC2H_REQ_MAPPING_0	0x2970
#define MC_MC_SMMU_PTC2H_REQ_MAPPING_0_PTC22H_REQ_MAPPING_RANGE	9:8
#define MC_MC_SMMU_PTC2H_REQ_MAPPING_OVERRIDE_0	0x296c
#define MC_MC_SMMU_PTC2H_REQ_MAPPING_OVERRIDE_0_PTC22H_REQ_MAPPING_OVERRIDE_ENABLE	1
#define MC_MC_SMMU_PTC2H_REQ_MAPPING_OVERRIDE_0_PTC22H_REQ_MAPPING_OVERRIDE_RANGE	8:8
#define MC_MIU0_PTSA_MAX_0	0x3144
#define MC_MIU0_PTSA_MAX_0_PTSA_MAX_MIU0_DEFAULT_MASK	0x7ff
#define MC_MIU0_PTSA_MIN_0	0x3140
#define MC_MIU0_PTSA_MIN_0_PTSA_MIN_MIU0_DEFAULT_MASK	0x7ff
#define MC_MIU0_PTSA_RATE_0	0x313c
#define MC_MIU0_PTSA_RATE_0_PTSA_RATE_MIU0_DEFAULT_MASK	0xfff
#define MC_MIU1_PTSA_MAX_0	0x3150
#define MC_MIU1_PTSA_MAX_0_PTSA_MAX_MIU1_DEFAULT_MASK	0x7ff
#define MC_MIU1_PTSA_MIN_0	0x314c
#define MC_MIU1_PTSA_MIN_0_PTSA_MIN_MIU1_DEFAULT_MASK	0x7ff
#define MC_MIU1_PTSA_RATE_0	0x3148
#define MC_MIU1_PTSA_RATE_0_PTSA_RATE_MIU1_DEFAULT_MASK	0xfff
#define MC_MIU2_PTSA_MAX_0	0x315c
#define MC_MIU2_PTSA_MAX_0_PTSA_MAX_MIU2_DEFAULT_MASK	0x7ff
#define MC_MIU2_PTSA_MIN_0	0x3158
#define MC_MIU2_PTSA_MIN_0_PTSA_MIN_MIU2_DEFAULT_MASK	0x7ff
#define MC_MIU2_PTSA_RATE_0	0x3154
#define MC_MIU2_PTSA_RATE_0_PTSA_RATE_MIU2_DEFAULT_MASK	0xfff
#define MC_MIU3_PTSA_MAX_0	0x3168
#define MC_MIU3_PTSA_MAX_0_PTSA_MAX_MIU3_DEFAULT_MASK	0x7ff
#define MC_MIU3_PTSA_MIN_0	0x3164
#define MC_MIU3_PTSA_MIN_0_PTSA_MIN_MIU3_DEFAULT_MASK	0x7ff
#define MC_MIU3_PTSA_RATE_0	0x3160
#define MC_MIU3_PTSA_RATE_0_PTSA_RATE_MIU3_DEFAULT_MASK	0xfff
#define MC_MIU4_PTSA_MAX_0	0x4b44
#define MC_MIU4_PTSA_MAX_0_PTSA_MAX_MIU4_DEFAULT_MASK	0x7ff
#define MC_MIU4_PTSA_MIN_0	0x4b40
#define MC_MIU4_PTSA_MIN_0_PTSA_MIN_MIU4_DEFAULT_MASK	0x7ff
#define MC_MIU4_PTSA_RATE_0	0x4b3c
#define MC_MIU4_PTSA_RATE_0_PTSA_RATE_MIU4_DEFAULT_MASK	0xfff
#define MC_MIU5_PTSA_MAX_0	0x4b50
#define MC_MIU5_PTSA_MAX_0_PTSA_MAX_MIU5_DEFAULT_MASK	0x7ff
#define MC_MIU5_PTSA_MIN_0	0x4b4c
#define MC_MIU5_PTSA_MIN_0_PTSA_MIN_MIU5_DEFAULT_MASK	0x7ff
#define MC_MIU5_PTSA_RATE_0	0x4b48
#define MC_MIU5_PTSA_RATE_0_PTSA_RATE_MIU5_DEFAULT_MASK	0xfff
#define MC_MIU6_PTSA_MAX_0	0x4b5c
#define MC_MIU6_PTSA_MAX_0_PTSA_MAX_MIU6_DEFAULT_MASK	0x7ff
#define MC_MIU6_PTSA_MIN_0	0x4b58
#define MC_MIU6_PTSA_MIN_0_PTSA_MIN_MIU6_DEFAULT_MASK	0x7ff
#define MC_MIU6_PTSA_RATE_0	0x4b54
#define MC_MIU6_PTSA_RATE_0_PTSA_RATE_MIU6_DEFAULT_MASK	0xfff
#define MC_MIU7_PTSA_MAX_0	0x4b68
#define MC_MIU7_PTSA_MAX_0_PTSA_MAX_MIU7_DEFAULT_MASK	0x7ff
#define MC_MIU7_PTSA_MIN_0	0x4b64
#define MC_MIU7_PTSA_MIN_0_PTSA_MIN_MIU7_DEFAULT_MASK	0x7ff
#define MC_MIU7_PTSA_RATE_0	0x4b60
#define MC_MIU7_PTSA_RATE_0_PTSA_RATE_MIU7_DEFAULT_MASK	0xfff
#define MC_MLL_MPCORER_PTSA_MAX_0	0x454
#define MC_MLL_MPCORER_PTSA_MAX_0_PTSA_MAX_MLL_MPCORER_DEFAULT_MASK	0x7ff
#define MC_MLL_MPCORER_PTSA_MIN_0	0x450
#define MC_MLL_MPCORER_PTSA_MIN_0_PTSA_MIN_MLL_MPCORER_DEFAULT_MASK	0x7ff
#define MC_MLL_MPCORER_PTSA_RATE_0	0x44c
#define MC_MLL_MPCORER_PTSA_RATE_0_PTSA_RATE_MLL_MPCORER_DEFAULT_MASK	0xfff
#define MC_MSE2_PTSA_MAX_0	0x7d0
#define MC_MSE2_PTSA_MAX_0_PTSA_MAX_MSE2_DEFAULT_MASK	0x7ff
#define MC_MSE2_PTSA_MIN_0	0x7cc
#define MC_MSE2_PTSA_MIN_0_PTSA_MIN_MSE2_DEFAULT_MASK	0x7ff
#define MC_MSE2_PTSA_RATE_0	0x7c8
#define MC_MSE2_PTSA_RATE_0_PTSA_RATE_MSE2_DEFAULT_MASK	0xfff
#define MC_MSE3_PTSA_MAX_0	0x3138
#define MC_MSE3_PTSA_MAX_0_PTSA_MAX_MSE3_DEFAULT_MASK	0x7ff
#define MC_MSE3_PTSA_MIN_0	0x3134
#define MC_MSE3_PTSA_MIN_0_PTSA_MIN_MSE3_DEFAULT_MASK	0x7ff
#define MC_MSE3_PTSA_RATE_0	0x3130
#define MC_MSE3_PTSA_RATE_0_PTSA_RATE_MSE3_DEFAULT_MASK	0xfff
#define MC_MSEA_PTSA_MAX_0	0x3a50
#define MC_MSEA_PTSA_MAX_0_PTSA_MAX_MSEA_DEFAULT_MASK	0x7ff
#define MC_MSEA_PTSA_MIN_0	0x3a4c
#define MC_MSEA_PTSA_MIN_0_PTSA_MIN_MSEA_DEFAULT_MASK	0x7ff
#define MC_MSEA_PTSA_RATE_0	0x3a48
#define MC_MSEA_PTSA_RATE_0_PTSA_RATE_MSEA_DEFAULT_MASK	0xfff
#define MC_MSEB1_PTSA_MAX_0	0x3a68
#define MC_MSEB1_PTSA_MAX_0_PTSA_MAX_MSEB1_DEFAULT_MASK	0x7ff
#define MC_MSEB1_PTSA_MIN_0	0x3a64
#define MC_MSEB1_PTSA_MIN_0_PTSA_MIN_MSEB1_DEFAULT_MASK	0x7ff
#define MC_MSEB1_PTSA_RATE_0	0x3a60
#define MC_MSEB1_PTSA_RATE_0_PTSA_RATE_MSEB1_DEFAULT_MASK	0xfff
#define MC_MSEB_PTSA_MAX_0	0x3a5c
#define MC_MSEB_PTSA_MAX_0_PTSA_MAX_MSEB_DEFAULT_MASK	0x7ff
#define MC_MSEB_PTSA_MIN_0	0x3a58
#define MC_MSEB_PTSA_MIN_0_PTSA_MIN_MSEB_DEFAULT_MASK	0x7ff
#define MC_MSEB_PTSA_RATE_0	0x3a54
#define MC_MSEB_PTSA_RATE_0_PTSA_RATE_MSEB_DEFAULT_MASK	0xfff
#define MC_MSE_PTSA_MAX_0	0x4cc
#define MC_MSE_PTSA_MAX_0_PTSA_MAX_MSE_DEFAULT_MASK	0x7ff
#define MC_MSE_PTSA_MIN_0	0x4c8
#define MC_MSE_PTSA_MIN_0_PTSA_MIN_MSE_DEFAULT_MASK	0x7ff
#define MC_MSE_PTSA_RATE_0	0x4c4
#define MC_MSE_PTSA_RATE_0_PTSA_RATE_MSE_DEFAULT_MASK	0xfff
#define MC_MSSNVLINK_DGPU_LATENCY_ALLOWANCE_0	0x1894
#define MC_MSSNVLINK_IGPU_LATENCY_ALLOWANCE_0	0x1890
#define MC_NIC_PTSA_MAX_0	0x740
#define MC_NIC_PTSA_MAX_0_PTSA_MAX_NIC_DEFAULT_MASK	0x7ff
#define MC_NIC_PTSA_MIN_0	0x73c
#define MC_NIC_PTSA_MIN_0_PTSA_MIN_NIC_DEFAULT_MASK	0x7ff
#define MC_NIC_PTSA_RATE_0	0x738
#define MC_NIC_PTSA_RATE_0_PTSA_RATE_NIC_DEFAULT_MASK	0xfff
#define MC_NVD2_PTSA_MAX_0	0x3a20
#define MC_NVD2_PTSA_MAX_0_PTSA_MAX_NVD2_DEFAULT_MASK	0x7ff
#define MC_NVD2_PTSA_MIN_0	0x3a1c
#define MC_NVD2_PTSA_MIN_0_PTSA_MIN_NVD2_DEFAULT_MASK	0x7ff
#define MC_NVD2_PTSA_RATE_0	0x3a18
#define MC_NVD2_PTSA_RATE_0_PTSA_RATE_NVD2_DEFAULT_MASK	0xfff
#define MC_NVD3_PTSA_MAX_0	0x7c4
#define MC_NVD3_PTSA_MAX_0_PTSA_MAX_NVD3_DEFAULT_MASK	0x7ff
#define MC_NVD3_PTSA_MIN_0	0x7c0
#define MC_NVD3_PTSA_MIN_0_PTSA_MIN_NVD3_DEFAULT_MASK	0x7ff
#define MC_NVD3_PTSA_RATE_0	0x7bc
#define MC_NVD3_PTSA_RATE_0_PTSA_RATE_NVD3_DEFAULT_MASK	0xfff
#define MC_NVD4_PTSA_MAX_0	0x4b20
#define MC_NVD4_PTSA_MAX_0_PTSA_MAX_NVD4_DEFAULT_MASK	0x7ff
#define MC_NVD4_PTSA_MIN_0	0x4b1c
#define MC_NVD4_PTSA_MIN_0_PTSA_MIN_NVD4_DEFAULT_MASK	0x7ff
#define MC_NVD4_PTSA_RATE_0	0x4b18
#define MC_NVD4_PTSA_RATE_0_PTSA_RATE_NVD4_DEFAULT_MASK	0xfff
#define MC_NVD5_PTSA_MAX_0	0x4b2c
#define MC_NVD5_PTSA_MAX_0_PTSA_MAX_NVD5_DEFAULT_MASK	0x7ff
#define MC_NVD5_PTSA_MIN_0	0x4b28
#define MC_NVD5_PTSA_MIN_0_PTSA_MIN_NVD5_DEFAULT_MASK	0x7ff
#define MC_NVD5_PTSA_RATE_0	0x4b24
#define MC_NVD5_PTSA_RATE_0_PTSA_RATE_NVD5_DEFAULT_MASK	0xfff
#define MC_NVD6_PTSA_MAX_0	0x4b38
#define MC_NVD6_PTSA_MAX_0_PTSA_MAX_NVD6_DEFAULT_MASK	0x7ff
#define MC_NVD6_PTSA_MIN_0	0x4b34
#define MC_NVD6_PTSA_MIN_0_PTSA_MIN_NVD6_DEFAULT_MASK	0x7ff
#define MC_NVD6_PTSA_RATE_0	0x4b30
#define MC_NVD6_PTSA_RATE_0_PTSA_RATE_NVD6_DEFAULT_MASK	0xfff
#define MC_NVD_PTSA_MAX_0	0x580
#define MC_NVD_PTSA_MAX_0_PTSA_MAX_NVD_DEFAULT_MASK	0x7ff
#define MC_NVD_PTSA_MIN_0	0x57c
#define MC_NVD_PTSA_MIN_0_PTSA_MIN_NVD_DEFAULT_MASK	0x7ff
#define MC_NVD_PTSA_RATE_0	0x578
#define MC_NVD_PTSA_RATE_0_PTSA_RATE_NVD_DEFAULT_MASK	0xfff
#define MC_PCFIFO_CLIENT_CONFIG0_0	0xdd0
#define MC_PCFIFO_CLIENT_CONFIG1_0	0xdd4
#define MC_PCFIFO_CLIENT_CONFIG1_0_PCFIFO_HDAW_ORDERED_CLIENT_ORDERED	1
#define MC_PCFIFO_CLIENT_CONFIG1_0_PCFIFO_HDAW_ORDERED_CLIENT_RANGE	21:21
#define MC_PCFIFO_CLIENT_CONFIG1_0_PCFIFO_SATAW_ORDERED_CLIENT_ORDERED	1
#define MC_PCFIFO_CLIENT_CONFIG1_0_PCFIFO_SATAW_ORDERED_CLIENT_RANGE	29:29
#define MC_PCFIFO_CLIENT_CONFIG2_0	0xdd8
#define MC_PCFIFO_CLIENT_CONFIG2_0_PCFIFO_XUSB_DEVW_ORDERED_CLIENT_ORDERED	1
#define MC_PCFIFO_CLIENT_CONFIG2_0_PCFIFO_XUSB_DEVW_ORDERED_CLIENT_RANGE	13:13
#define MC_PCFIFO_CLIENT_CONFIG3_0	0xddc
#define MC_PCFIFO_CLIENT_CONFIG4_0	0xde0
#define MC_PCFIFO_CLIENT_CONFIG5_0	0xbf4
#define MC_PCFIFO_CLIENT_CONFIG6_0	0xb90
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE1W_ORDERED_CLIENT_ORDERED	1
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE1W_ORDERED_CLIENT_RANGE	27:27
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE1W_ORDERED_CLIENT_UNORDERED	0
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE2AW_ORDERED_CLIENT_ORDERED	1
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE2AW_ORDERED_CLIENT_RANGE	29:29
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE2AW_ORDERED_CLIENT_UNORDERED	0
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE3W_ORDERED_CLIENT_ORDERED	1
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE3W_ORDERED_CLIENT_RANGE	31:31
#define MC_PCFIFO_CLIENT_CONFIG6_0_PCFIFO_PCIE3W_ORDERED_CLIENT_UNORDERED	0
#define MC_PCFIFO_CLIENT_CONFIG7_0	0xacc
#define MC_PCIE0X2_PTSA_MAX_0	0x4b14
#define MC_PCIE0X2_PTSA_MAX_0_PTSA_MAX_PCIE0X2_DEFAULT_MASK	0x7ff
#define MC_PCIE0X2_PTSA_MIN_0	0x4b10
#define MC_PCIE0X2_PTSA_MIN_0_PTSA_MIN_PCIE0X2_DEFAULT_MASK	0x7ff
#define MC_PCIE0X2_PTSA_RATE_0	0x4b0c
#define MC_PCIE0X2_PTSA_RATE_0_PTSA_RATE_PCIE0X2_DEFAULT_MASK	0xfff
#define MC_PCIE0XA_PTSA_MAX_0	0x3508
#define MC_PCIE0XA_PTSA_MAX_0_PTSA_MAX_PCIE0XA_DEFAULT_MASK	0x7ff
#define MC_PCIE0XA_PTSA_MIN_0	0x3504
#define MC_PCIE0XA_PTSA_MIN_0_PTSA_MIN_PCIE0XA_DEFAULT_MASK	0x7ff
#define MC_PCIE0XA_PTSA_RATE_0	0x3500
#define MC_PCIE0XA_PTSA_RATE_0_PTSA_RATE_PCIE0XA_DEFAULT_MASK	0xfff
#define MC_PCIE0X_PTSA_MAX_0	0x3314
#define MC_PCIE0X_PTSA_MAX_0_PTSA_MAX_PCIE0X_DEFAULT_MASK	0x7ff
#define MC_PCIE0X_PTSA_MIN_0	0x3310
#define MC_PCIE0X_PTSA_MIN_0_PTSA_MIN_PCIE0X_DEFAULT_MASK	0x7ff
#define MC_PCIE0X_PTSA_RATE_0	0x330c
#define MC_PCIE0X_PTSA_RATE_0_PTSA_RATE_PCIE0X_DEFAULT_MASK	0xfff
#define MC_PCIE1XA_PTSA_MAX_0	0x3514
#define MC_PCIE1XA_PTSA_MAX_0_PTSA_MAX_PCIE1XA_DEFAULT_MASK	0x7ff
#define MC_PCIE1XA_PTSA_MIN_0	0x3510
#define MC_PCIE1XA_PTSA_MIN_0_PTSA_MIN_PCIE1XA_DEFAULT_MASK	0x7ff
#define MC_PCIE1XA_PTSA_RATE_0	0x350c
#define MC_PCIE1XA_PTSA_RATE_0_PTSA_RATE_PCIE1XA_DEFAULT_MASK	0xfff
#define MC_PCIE1X_PTSA_MAX_0	0x3320
#define MC_PCIE1X_PTSA_MAX_0_PTSA_MAX_PCIE1X_DEFAULT_MASK	0x7ff
#define MC_PCIE1X_PTSA_MIN_0	0x331c
#define MC_PCIE1X_PTSA_MIN_0_PTSA_MIN_PCIE1X_DEFAULT_MASK	0x7ff
#define MC_PCIE1X_PTSA_RATE_0	0x3318
#define MC_PCIE1X_PTSA_RATE_0_PTSA_RATE_PCIE1X_DEFAULT_MASK	0xfff
#define MC_PCIE4XA_PTSA_MAX_0	0x3538
#define MC_PCIE4XA_PTSA_MAX_0_PTSA_MAX_PCIE4XA_DEFAULT_MASK	0x7ff
#define MC_PCIE4XA_PTSA_MIN_0	0x3534
#define MC_PCIE4XA_PTSA_MIN_0_PTSA_MIN_PCIE4XA_DEFAULT_MASK	0x7ff
#define MC_PCIE4XA_PTSA_RATE_0	0x3530
#define MC_PCIE4XA_PTSA_RATE_0_PTSA_RATE_PCIE4XA_DEFAULT_MASK	0xfff
#define MC_PCIE4X_PTSA_MAX_0	0x3344
#define MC_PCIE4X_PTSA_MAX_0_PTSA_MAX_PCIE4X_DEFAULT_MASK	0x7ff
#define MC_PCIE4X_PTSA_MIN_0	0x3340
#define MC_PCIE4X_PTSA_MIN_0_PTSA_MIN_PCIE4X_DEFAULT_MASK	0x7ff
#define MC_PCIE4X_PTSA_RATE_0	0x333c
#define MC_PCIE4X_PTSA_RATE_0_PTSA_RATE_PCIE4X_DEFAULT_MASK	0xfff
#define MC_PCIE5X2_PTSA_MAX_0	0x3a08
#define MC_PCIE5X2_PTSA_MAX_0_PTSA_MAX_PCIE5X2_DEFAULT_MASK	0x7ff
#define MC_PCIE5X2_PTSA_MIN_0	0x3a04
#define MC_PCIE5X2_PTSA_MIN_0_PTSA_MIN_PCIE5X2_DEFAULT_MASK	0x7ff
#define MC_PCIE5X2_PTSA_RATE_0	0x3a00
#define MC_PCIE5X2_PTSA_RATE_0_PTSA_RATE_PCIE5X2_DEFAULT_MASK	0xfff
#define MC_PCIE5XA_PTSA_MAX_0	0x3544
#define MC_PCIE5XA_PTSA_MAX_0_PTSA_MAX_PCIE5XA_DEFAULT_MASK	0x7ff
#define MC_PCIE5XA_PTSA_MIN_0	0x3540
#define MC_PCIE5XA_PTSA_MIN_0_PTSA_MIN_PCIE5XA_DEFAULT_MASK	0x7ff
#define MC_PCIE5XA_PTSA_RATE_0	0x353c
#define MC_PCIE5XA_PTSA_RATE_0_PTSA_RATE_PCIE5XA_DEFAULT_MASK	0xfff
#define MC_PCIE5X_PTSA_MAX_0	0x3350
#define MC_PCIE5X_PTSA_MAX_0_PTSA_MAX_PCIE5X_DEFAULT_MASK	0x7ff
#define MC_PCIE5X_PTSA_MIN_0	0x334c
#define MC_PCIE5X_PTSA_MIN_0_PTSA_MIN_PCIE5X_DEFAULT_MASK	0x7ff
#define MC_PCIE5X_PTSA_RATE_0	0x3348
#define MC_PCIE5X_PTSA_RATE_0_PTSA_RATE_PCIE5X_DEFAULT_MASK	0xfff
#define MC_PTSA_MINMAX_DEFAULT_MASK 0x3f
#define MC_PVA0XA2_PTSA_MAX_0	0x3950
#define MC_PVA0XA2_PTSA_MAX_0_PTSA_MAX_PVA0XA2_DEFAULT_MASK	0x7ff
#define MC_PVA0XA2_PTSA_MIN_0	0x394c
#define MC_PVA0XA2_PTSA_MIN_0_PTSA_MIN_PVA0XA2_DEFAULT_MASK	0x7ff
#define MC_PVA0XA2_PTSA_RATE_0	0x3948
#define MC_PVA0XA2_PTSA_RATE_0_PTSA_RATE_PVA0XA2_DEFAULT_MASK	0xfff
#define MC_PVA0XA3_PTSA_MAX_0	0x3550
#define MC_PVA0XA3_PTSA_MAX_0_PTSA_MAX_PVA0XA3_DEFAULT_MASK	0x7ff
#define MC_PVA0XA3_PTSA_MIN_0	0x354c
#define MC_PVA0XA3_PTSA_MIN_0_PTSA_MIN_PVA0XA3_DEFAULT_MASK	0x7ff
#define MC_PVA0XA3_PTSA_RATE_0	0x3548
#define MC_PVA0XA3_PTSA_RATE_0_PTSA_RATE_PVA0XA3_DEFAULT_MASK	0xfff
#define MC_PVA0XA_PTSA_MAX_0	0x3108
#define MC_PVA0XA_PTSA_MAX_0_PTSA_MAX_PVA0XA_DEFAULT_MASK	0x7ff
#define MC_PVA0XA_PTSA_MIN_0	0x3104
#define MC_PVA0XA_PTSA_MIN_0_PTSA_MIN_PVA0XA_DEFAULT_MASK	0x7ff
#define MC_PVA0XA_PTSA_RATE_0	0x3100
#define MC_PVA0XA_PTSA_RATE_0_PTSA_RATE_PVA0XA_DEFAULT_MASK	0xfff
#define MC_PVA0XB2_PTSA_MAX_0	0x395c
#define MC_PVA0XB2_PTSA_MAX_0_PTSA_MAX_PVA0XB2_DEFAULT_MASK	0x7ff
#define MC_PVA0XB2_PTSA_MIN_0	0x3958
#define MC_PVA0XB2_PTSA_MIN_0_PTSA_MIN_PVA0XB2_DEFAULT_MASK	0x7ff
#define MC_PVA0XB2_PTSA_RATE_0	0x3954
#define MC_PVA0XB2_PTSA_RATE_0_PTSA_RATE_PVA0XB2_DEFAULT_MASK	0xfff
#define MC_PVA0XB3_PTSA_MAX_0	0x3568
#define MC_PVA0XB3_PTSA_MAX_0_PTSA_MAX_PVA0XB3_DEFAULT_MASK	0x7ff
#define MC_PVA0XB3_PTSA_MIN_0	0x3564
#define MC_PVA0XB3_PTSA_MIN_0_PTSA_MIN_PVA0XB3_DEFAULT_MASK	0x7ff
#define MC_PVA0XB3_PTSA_RATE_0	0x3560
#define MC_PVA0XB3_PTSA_RATE_0_PTSA_RATE_PVA0XB3_DEFAULT_MASK	0xfff
#define MC_PVA0XB_PTSA_MAX_0	0x355c
#define MC_PVA0XB_PTSA_MAX_0_PTSA_MAX_PVA0XB_DEFAULT_MASK	0x7ff
#define MC_PVA0XB_PTSA_MIN_0	0x3558
#define MC_PVA0XB_PTSA_MIN_0_PTSA_MIN_PVA0XB_DEFAULT_MASK	0x7ff
#define MC_PVA0XB_PTSA_RATE_0	0x3554
#define MC_PVA0XB_PTSA_RATE_0_PTSA_RATE_PVA0XB_DEFAULT_MASK	0xfff
#define MC_PVA0XC_PTSA_MAX_0	0x3574
#define MC_PVA0XC_PTSA_MAX_0_PTSA_MAX_PVA0XC_DEFAULT_MASK	0x7ff
#define MC_PVA0XC_PTSA_MIN_0	0x3570
#define MC_PVA0XC_PTSA_MIN_0_PTSA_MIN_PVA0XC_DEFAULT_MASK	0x7ff
#define MC_PVA0XC_PTSA_RATE_0	0x356c
#define MC_PVA0XC_PTSA_RATE_0_PTSA_RATE_PVA0XC_DEFAULT_MASK	0xfff
#define MC_PVA1XA2_PTSA_MAX_0	0x3968
#define MC_PVA1XA2_PTSA_MAX_0_PTSA_MAX_PVA1XA2_DEFAULT_MASK	0x7ff
#define MC_PVA1XA2_PTSA_MIN_0	0x3964
#define MC_PVA1XA2_PTSA_MIN_0_PTSA_MIN_PVA1XA2_DEFAULT_MASK	0x7ff
#define MC_PVA1XA2_PTSA_RATE_0	0x3960
#define MC_PVA1XA2_PTSA_RATE_0_PTSA_RATE_PVA1XA2_DEFAULT_MASK	0xfff
#define MC_PVA1XA3_PTSA_MAX_0	0x3908
#define MC_PVA1XA3_PTSA_MAX_0_PTSA_MAX_PVA1XA3_DEFAULT_MASK	0x7ff
#define MC_PVA1XA3_PTSA_MIN_0	0x3904
#define MC_PVA1XA3_PTSA_MIN_0_PTSA_MIN_PVA1XA3_DEFAULT_MASK	0x7ff
#define MC_PVA1XA3_PTSA_RATE_0	0x3900
#define MC_PVA1XA3_PTSA_RATE_0_PTSA_RATE_PVA1XA3_DEFAULT_MASK	0xfff
#define MC_PVA1XA_PTSA_MAX_0	0x3114
#define MC_PVA1XA_PTSA_MAX_0_PTSA_MAX_PVA1XA_DEFAULT_MASK	0x7ff
#define MC_PVA1XA_PTSA_MIN_0	0x3110
#define MC_PVA1XA_PTSA_MIN_0_PTSA_MIN_PVA1XA_DEFAULT_MASK	0x7ff
#define MC_PVA1XA_PTSA_RATE_0	0x310c
#define MC_PVA1XA_PTSA_RATE_0_PTSA_RATE_PVA1XA_DEFAULT_MASK	0xfff
#define MC_PVA1XB2_PTSA_MAX_0	0x3974
#define MC_PVA1XB2_PTSA_MAX_0_PTSA_MAX_PVA1XB2_DEFAULT_MASK	0x7ff
#define MC_PVA1XB2_PTSA_MIN_0	0x3970
#define MC_PVA1XB2_PTSA_MIN_0_PTSA_MIN_PVA1XB2_DEFAULT_MASK	0x7ff
#define MC_PVA1XB2_PTSA_RATE_0	0x396c
#define MC_PVA1XB2_PTSA_RATE_0_PTSA_RATE_PVA1XB2_DEFAULT_MASK	0xfff
#define MC_PVA1XB3_PTSA_MAX_0	0x3920
#define MC_PVA1XB3_PTSA_MAX_0_PTSA_MAX_PVA1XB3_DEFAULT_MASK	0x7ff
#define MC_PVA1XB3_PTSA_MIN_0	0x391c
#define MC_PVA1XB3_PTSA_MIN_0_PTSA_MIN_PVA1XB3_DEFAULT_MASK	0x7ff
#define MC_PVA1XB3_PTSA_RATE_0	0x3918
#define MC_PVA1XB3_PTSA_RATE_0_PTSA_RATE_PVA1XB3_DEFAULT_MASK	0xfff
#define MC_PVA1XB_PTSA_MAX_0	0x3914
#define MC_PVA1XB_PTSA_MAX_0_PTSA_MAX_PVA1XB_DEFAULT_MASK	0x7ff
#define MC_PVA1XB_PTSA_MIN_0	0x3910
#define MC_PVA1XB_PTSA_MIN_0_PTSA_MIN_PVA1XB_DEFAULT_MASK	0x7ff
#define MC_PVA1XB_PTSA_RATE_0	0x390c
#define MC_PVA1XB_PTSA_RATE_0_PTSA_RATE_PVA1XB_DEFAULT_MASK	0xfff
#define MC_PVA1XC_PTSA_MAX_0	0x392c
#define MC_PVA1XC_PTSA_MAX_0_PTSA_MAX_PVA1XC_DEFAULT_MASK	0x7ff
#define MC_PVA1XC_PTSA_MIN_0	0x3928
#define MC_PVA1XC_PTSA_MIN_0_PTSA_MIN_PVA1XC_DEFAULT_MASK	0x7ff
#define MC_PVA1XC_PTSA_RATE_0	0x3924
#define MC_PVA1XC_PTSA_RATE_0_PTSA_RATE_PVA1XC_DEFAULT_MASK	0xfff
#define MC_RCEPC_PTSA_MAX_0	0x3120
#define MC_RCEPC_PTSA_MAX_0_PTSA_MAX_RCEPC_DEFAULT_MASK	0x7ff
#define MC_RCEPC_PTSA_MIN_0	0x311c
#define MC_RCEPC_PTSA_MIN_0_PTSA_MIN_RCEPC_DEFAULT_MASK	0x7ff
#define MC_RCEPC_PTSA_RATE_0	0x3118
#define MC_RCEPC_PTSA_RATE_0_PTSA_RATE_RCEPC_DEFAULT_MASK	0xfff
#define MC_RING1_PTSA_RATE_0_PTSA_RATE_RING1_DEFAULT_MASK	0xfff
#define MC_RING1_RD_B_PTSA_RATE_0_PTSA_RATE_RING1_RD_B_DEFAULT_MASK	0xfff
#define MC_RING1_RD_NB_PTSA_RATE_0_PTSA_RATE_RING1_RD_NB_DEFAULT_MASK	0xfff
#define MC_RING1_WR_B_PTSA_RATE_0_PTSA_RATE_RING1_WR_B_DEFAULT_MASK	0xfff
#define MC_RING1_WR_NB_PTSA_RATE_0_PTSA_RATE_RING1_WR_NB_DEFAULT_MASK	0xfff
#define MC_RING2_PTSA_MAX_0	0x448
#define MC_RING2_PTSA_MAX_0_PTSA_MAX_RING2_DEFAULT_MASK	0x7ff
#define MC_RING2_PTSA_MIN_0	0x444
#define MC_RING2_PTSA_MIN_0_PTSA_MIN_RING2_DEFAULT_MASK	0x7ff
#define MC_RING2_PTSA_RATE_0	0x440
#define MC_RING2_PTSA_RATE_0_PTSA_RATE_RING2_DEFAULT_MASK	0xfff
#define MC_ROC_DMA_R_PTSA_RATE_0_PTSA_RATE_ROC_DMA_R_DEFAULT_MASK	0xfff
#define MC_SAX_PTSA_MAX_0	0x4c0
#define MC_SAX_PTSA_MAX_0_PTSA_MAX_SAX_DEFAULT_MASK	0x7ff
#define MC_SAX_PTSA_MIN_0	0x4bc
#define MC_SAX_PTSA_MIN_0_PTSA_MIN_SAX_DEFAULT_MASK	0x7ff
#define MC_SAX_PTSA_RATE_0	0x4b8
#define MC_SAX_PTSA_RATE_0_PTSA_RATE_SAX_DEFAULT_MASK	0xfff
#define MC_SCEPC_PTSA_MAX_0	0x794
#define MC_SCEPC_PTSA_MAX_0_PTSA_MAX_SCEPC_DEFAULT_MASK	0x7ff
#define MC_SCEPC_PTSA_MIN_0	0x790
#define MC_SCEPC_PTSA_MIN_0_PTSA_MIN_SCEPC_DEFAULT_MASK	0x7ff
#define MC_SCEPC_PTSA_RATE_0	0x78c
#define MC_SCEPC_PTSA_RATE_0_PTSA_RATE_SCEPC_DEFAULT_MASK	0xfff
#define MC_SDM_PTSA_MAX_0	0x624
#define MC_SDM_PTSA_MAX_0_PTSA_MAX_SDM_DEFAULT_MASK	0x7ff
#define MC_SDM_PTSA_MIN_0	0x620
#define MC_SDM_PTSA_MIN_0_PTSA_MIN_SDM_DEFAULT_MASK	0x7ff
#define MC_SDM_PTSA_RATE_0	0x61c
#define MC_SDM_PTSA_RATE_0_PTSA_RATE_SDM_DEFAULT_MASK	0xfff
#define MC_SD_PTSA_MAX_0	0x4d8
#define MC_SD_PTSA_MAX_0_PTSA_MAX_SD_DEFAULT_MASK	0x7ff
#define MC_SD_PTSA_MIN_0	0x4d4
#define MC_SD_PTSA_MIN_0_PTSA_MIN_SD_DEFAULT_MASK	0x7ff
#define MC_SD_PTSA_RATE_0	0x4d0
#define MC_SD_PTSA_RATE_0_PTSA_RATE_SD_DEFAULT_MASK	0xfff
#define MC_SMMU_SMMU_PTSA_MAX_0	0x460
#define MC_SMMU_SMMU_PTSA_MAX_0_PTSA_MAX_SMMU_SMMU_DEFAULT_MASK	0x7ff
#define MC_SMMU_SMMU_PTSA_MIN_0	0x45c
#define MC_SMMU_SMMU_PTSA_MIN_0_PTSA_MIN_SMMU_SMMU_DEFAULT_MASK	0x7ff
#define MC_SMMU_SMMU_PTSA_RATE_0	0x458
#define MC_SMMU_SMMU_PTSA_RATE_0_PTSA_RATE_SMMU_SMMU_DEFAULT_MASK	0xfff
#define MC_TBU_CLIENT_STEERING_CONFIG_AONDMAR_0	0x14cc
#define MC_TBU_CLIENT_STEERING_CONFIG_AONDMAW_0	0x14d4
#define MC_TBU_CLIENT_STEERING_CONFIG_AONR_0	0x14bc
#define MC_TBU_CLIENT_STEERING_CONFIG_AONW_0	0x14c4
#define MC_TBU_CLIENT_STEERING_CONFIG_APEDMAR_0	0x14fc
#define MC_TBU_CLIENT_STEERING_CONFIG_APEDMAW_0	0x1504
#define MC_TBU_CLIENT_STEERING_CONFIG_APER_0	0x13d4
#define MC_TBU_CLIENT_STEERING_CONFIG_APEW_0	0x13dc
#define MC_TBU_CLIENT_STEERING_CONFIG_AXIAPR_0	0x1414
#define MC_TBU_CLIENT_STEERING_CONFIG_AXIAPW_0	0x141c
#define MC_TBU_CLIENT_STEERING_CONFIG_AXISR_0	0x1464
#define MC_TBU_CLIENT_STEERING_CONFIG_AXISW_0	0x146c
#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPDMAR_0	0x14ac
#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPDMAW_0	0x14b4
#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPR_0	0x149c
#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPW_0	0x14a4
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0FALRDB_0	0x1600
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0FALWRB_0	0x1610
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0RDA1_0	0x1750
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0RDA_0	0x15f8
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0WRA_0	0x1608
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1FALRDB_0	0x1620
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1FALWRB_0	0x1630
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1RDA1_0	0x1758
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1RDA_0	0x1618
#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1WRA_0	0x1628
#define MC_TBU_CLIENT_STEERING_CONFIG_EQOSR_0	0x1474
#define MC_TBU_CLIENT_STEERING_CONFIG_EQOSW_0	0x147c
#define MC_TBU_CLIENT_STEERING_CONFIG_ETRR_0	0x1424
#define MC_TBU_CLIENT_STEERING_CONFIG_ETRW_0	0x142c
#define MC_TBU_CLIENT_STEERING_CONFIG_HDAR_0	0x10ac
#define MC_TBU_CLIENT_STEERING_CONFIG_HDAW_0	0x11ac
#define MC_TBU_CLIENT_STEERING_CONFIG_HOST1XDMAR_0	0x10b4
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPFALR_0	0x122c
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPFALW_0	0x1728
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPRA1_0	0x1798
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPRA_0	0x1224
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPWA_0	0x1234
#define MC_TBU_CLIENT_STEERING_CONFIG_ISPWB_0	0x123c
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU0R_0	0x1534
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU0W_0	0x153c
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU1R_0	0x1544
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU1W_0	0x154c
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU2R_0	0x1574
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU2W_0	0x157c
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU3R_0	0x1584
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU3W_0	0x1590
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU4R_0	0x1598
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU4W_0	0x15a0
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU5R_0	0x17e8
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU5W_0	0x17f0
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU6R_0	0x17f8
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU6W_0	0x4c00
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU7R_0	0x100c
#define MC_TBU_CLIENT_STEERING_CONFIG_MIU7W_0	0x1014
#define MC_TBU_CLIENT_STEERING_CONFIG_MPCORER_0	0x113c
#define MC_TBU_CLIENT_STEERING_CONFIG_MPCOREW_0	0x11cc
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SRD1_0	0x17d8
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SRD_0	0x17d0
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SWR_0	0x17e0
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSRD1_0	0x151c
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSRD_0	0x13c4
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSWR_0	0x13cc
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDISPLAYR1_0	0x150c
#define MC_TBU_CLIENT_STEERING_CONFIG_NVDISPLAYR_0	0x1494
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SRD1_0	0x1790
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SRD_0	0x16b8
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SWR_0	0x16c0
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSRD1_0	0x1788
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSRD_0	0x10e4
#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSWR_0	0x115c
#define MC_TBU_CLIENT_STEERING_CONFIG_NVJPGSRD_0	0x13f4
#define MC_TBU_CLIENT_STEERING_CONFIG_NVJPGSWR_0	0x13fc
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0R1_0	0x17a0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0R_0	0x16c8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0W_0	0x16d0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0W_0_PCIE0W_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0W_0_PCIE0W_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0W_0_PCIE0W_SO_DEV_TBUID_RANGE	9:8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1R_0	0x16d8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1W_0	0x16e0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1W_0_PCIE1W_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1W_0_PCIE1W_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1W_0_PCIE1W_SO_DEV_TBUID_RANGE	9:8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AR_0	0x16e8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AW_0	0x16f0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AW_0_PCIE2AW_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AW_0_PCIE2AW_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AW_0_PCIE2AW_SO_DEV_TBUID_RANGE	9:8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3R_0	0x16f8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3W_0	0x1700
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3W_0_PCIE3W_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3W_0_PCIE3W_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3W_0_PCIE3W_SO_DEV_TBUID_RANGE	9:8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4R_0	0x1708
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4W_0	0x1710
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4W_0_PCIE4W_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4W_0_PCIE4W_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4W_0_PCIE4W_SO_DEV_TBUID_RANGE	9:8
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5R1_0	0x1780
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5R_0	0x1718
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5W_0	0x1720
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5W_0_PCIE5W_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5W_0_PCIE5W_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5W_0_PCIE5W_SO_DEV_TBUID_RANGE	9:8
#define MC_TBU_CLIENT_STEERING_CONFIG_PTCR_0	0x1004
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDA1_0	0x1760
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDA_0	0x1638
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDB1_0	0x1768
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDB_0	0x1640
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDC_0	0x1648
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRA_0	0x1650
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRB_0	0x1658
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRC_0	0x1660
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDA1_0	0x1770
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDA_0	0x1668
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDB1_0	0x1778
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDB_0	0x1670
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDC_0	0x1678
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRA_0	0x1680
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRB_0	0x1688
#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRC_0	0x1690
#define MC_TBU_CLIENT_STEERING_CONFIG_RCEDMAR_0	0x16a8
#define MC_TBU_CLIENT_STEERING_CONFIG_RCEDMAW_0	0x16b0
#define MC_TBU_CLIENT_STEERING_CONFIG_RCER_0	0x1698
#define MC_TBU_CLIENT_STEERING_CONFIG_RCEW_0	0x16a0
#define MC_TBU_CLIENT_STEERING_CONFIG_SATAR_0	0x10fc
#define MC_TBU_CLIENT_STEERING_CONFIG_SATAW_0	0x11ec
#define MC_TBU_CLIENT_STEERING_CONFIG_SATAW_0_SATAW_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_SATAW_0_SATAW_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_SATAW_0_SATAW_SO_DEV_TBUID_RANGE	9:8
#define MC_TBU_CLIENT_STEERING_CONFIG_SCEDMAR_0	0x14ec
#define MC_TBU_CLIENT_STEERING_CONFIG_SCEDMAW_0	0x14f4
#define MC_TBU_CLIENT_STEERING_CONFIG_SCER_0	0x14dc
#define MC_TBU_CLIENT_STEERING_CONFIG_SCEW_0	0x14e4
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCRAB_0	0x131c
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCRA_0	0x1304
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCR_0	0x1314
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCWAB_0	0x133c
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCWA_0	0x1324
#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCW_0	0x1334
#define MC_TBU_CLIENT_STEERING_CONFIG_SESRD_0	0x1404
#define MC_TBU_CLIENT_STEERING_CONFIG_SESWR_0	0x140c
#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSRDB_0	0x1434
#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSRD_0	0x12a4
#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSWRB_0	0x143c
#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSWR_0	0x12ac
#define MC_TBU_CLIENT_STEERING_CONFIG_UFSHCR_0	0x1484
#define MC_TBU_CLIENT_STEERING_CONFIG_UFSHCW_0	0x148c
#define MC_TBU_CLIENT_STEERING_CONFIG_VICSRD1_0	0x1514
#define MC_TBU_CLIENT_STEERING_CONFIG_VICSRD_0	0x1364
#define MC_TBU_CLIENT_STEERING_CONFIG_VICSWR_0	0x136c
#define MC_TBU_CLIENT_STEERING_CONFIG_VIFALR_0	0x15e8
#define MC_TBU_CLIENT_STEERING_CONFIG_VIFALW_0	0x15f0
#define MC_TBU_CLIENT_STEERING_CONFIG_VIW_0	0x1394
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVR_0	0x1264
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVW_0	0x126c
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVW_0_XUSB_DEVW_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVW_0_XUSB_DEVW_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVW_0_XUSB_DEVW_SO_DEV_TBUID_RANGE	9:8
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTR_0	0x1254
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTW_0	0x125c
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTW_0_XUSB_HOSTW_NORMAL_TBUID_OVERRIDE_RANGE	0:0
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTW_0_XUSB_HOSTW_NORMAL_TBUID_RANGE	5:4
#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTW_0_XUSB_HOSTW_SO_DEV_TBUID_RANGE	9:8
#define MC_TIMING_CONTROL_0	0xfc
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR_0	0x14c8
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW_0	0x14d0
#define MC_TXN_OVERRIDE_CONFIG_AONR_0	0x14b8
#define MC_TXN_OVERRIDE_CONFIG_AONW_0	0x14c0
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR_0	0x14f8
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW_0	0x1500
#define MC_TXN_OVERRIDE_CONFIG_APER_0	0x13d0
#define MC_TXN_OVERRIDE_CONFIG_APEW_0	0x13d8
#define MC_TXN_OVERRIDE_CONFIG_AXIAPR_0	0x1410
#define MC_TXN_OVERRIDE_CONFIG_AXIAPW_0	0x1418
#define MC_TXN_OVERRIDE_CONFIG_AXISR_0	0x1460
#define MC_TXN_OVERRIDE_CONFIG_AXISW_0	0x1468
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR_0	0x14a8
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW_0	0x14b0
#define MC_TXN_OVERRIDE_CONFIG_BPMPR_0	0x1498
#define MC_TXN_OVERRIDE_CONFIG_BPMPW_0	0x14a0
#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB_0	0x15fc
#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB_0	0x160c
#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1_0	0x174c
#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA_0	0x15f4
#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA_0	0x1604
#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB_0	0x161c
#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB_0	0x162c
#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1_0	0x1754
#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA_0	0x1614
#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA_0	0x1624
#define MC_TXN_OVERRIDE_CONFIG_EQOSR_0	0x1470
#define MC_TXN_OVERRIDE_CONFIG_EQOSW_0	0x1478
#define MC_TXN_OVERRIDE_CONFIG_ETRR_0	0x1420
#define MC_TXN_OVERRIDE_CONFIG_ETRW_0	0x1428
#define MC_TXN_OVERRIDE_CONFIG_HDAR_0	0x10a8
#define MC_TXN_OVERRIDE_CONFIG_HDAW_0	0x11a8
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR_0	0x10b0
#define MC_TXN_OVERRIDE_CONFIG_ISPFALR_0	0x1228
#define MC_TXN_OVERRIDE_CONFIG_ISPFALW_0	0x1724
#define MC_TXN_OVERRIDE_CONFIG_ISPRA1_0	0x1794
#define MC_TXN_OVERRIDE_CONFIG_ISPRA_0	0x1220
#define MC_TXN_OVERRIDE_CONFIG_ISPWA_0	0x1230
#define MC_TXN_OVERRIDE_CONFIG_ISPWB_0	0x1238
#define MC_TXN_OVERRIDE_CONFIG_MIU0R_0	0x1530
#define MC_TXN_OVERRIDE_CONFIG_MIU0W_0	0x1538
#define MC_TXN_OVERRIDE_CONFIG_MIU1R_0	0x1540
#define MC_TXN_OVERRIDE_CONFIG_MIU1W_0	0x1548
#define MC_TXN_OVERRIDE_CONFIG_MIU2R_0	0x1570
#define MC_TXN_OVERRIDE_CONFIG_MIU2W_0	0x1578
#define MC_TXN_OVERRIDE_CONFIG_MIU3R_0	0x1580
#define MC_TXN_OVERRIDE_CONFIG_MIU3W_0	0x158c
#define MC_TXN_OVERRIDE_CONFIG_MIU4R_0	0x1594
#define MC_TXN_OVERRIDE_CONFIG_MIU4W_0	0x159c
#define MC_TXN_OVERRIDE_CONFIG_MIU5R_0	0x17e4
#define MC_TXN_OVERRIDE_CONFIG_MIU5W_0	0x17ec
#define MC_TXN_OVERRIDE_CONFIG_MIU6R_0	0x17f4
#define MC_TXN_OVERRIDE_CONFIG_MIU6W_0	0x17fc
#define MC_TXN_OVERRIDE_CONFIG_MIU7R_0	0x1008
#define MC_TXN_OVERRIDE_CONFIG_MIU7W_0	0x1010
#define MC_TXN_OVERRIDE_CONFIG_MPCORER_0	0x1138
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW_0	0x11c8
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1_0	0x17d4
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD_0	0x17cc
#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR_0	0x17dc
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1_0	0x1518
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD_0	0x13c0
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR_0	0x13c8
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1_0	0x1508
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR_0	0x1490
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1_0	0x178c
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD_0	0x16b4
#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR_0	0x16bc
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1_0	0x1784
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD_0	0x10e0
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR_0	0x1158
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD_0	0x13f0
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR_0	0x13f8
#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1_0	0x179c
#define MC_TXN_OVERRIDE_CONFIG_PCIE0R_0	0x16c4
#define MC_TXN_OVERRIDE_CONFIG_PCIE0W_0	0x16cc
#define MC_TXN_OVERRIDE_CONFIG_PCIE1R_0	0x16d4
#define MC_TXN_OVERRIDE_CONFIG_PCIE1W_0	0x16dc
#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR_0	0x16e4
#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW_0	0x16ec
#define MC_TXN_OVERRIDE_CONFIG_PCIE3R_0	0x16f4
#define MC_TXN_OVERRIDE_CONFIG_PCIE3W_0	0x16fc
#define MC_TXN_OVERRIDE_CONFIG_PCIE4R_0	0x1704
#define MC_TXN_OVERRIDE_CONFIG_PCIE4W_0	0x170c
#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1_0	0x177c
#define MC_TXN_OVERRIDE_CONFIG_PCIE5R_0	0x1714
#define MC_TXN_OVERRIDE_CONFIG_PCIE5W_0	0x171c
#define MC_TXN_OVERRIDE_CONFIG_PTCR_0	0x1000
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1_0	0x175c
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA_0	0x1634
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1_0	0x1764
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB_0	0x163c
#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC_0	0x1644
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA_0	0x164c
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB_0	0x1654
#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC_0	0x165c
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1_0	0x176c
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA_0	0x1664
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1_0	0x1774
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB_0	0x166c
#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC_0	0x1674
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA_0	0x167c
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB_0	0x1684
#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC_0	0x168c
#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR_0	0x16a4
#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW_0	0x16ac
#define MC_TXN_OVERRIDE_CONFIG_RCER_0	0x1694
#define MC_TXN_OVERRIDE_CONFIG_RCEW_0	0x169c
#define MC_TXN_OVERRIDE_CONFIG_SATAR_0	0x10f8
#define MC_TXN_OVERRIDE_CONFIG_SATAW_0	0x11e8
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR_0	0x14e8
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW_0	0x14f0
#define MC_TXN_OVERRIDE_CONFIG_SCER_0	0x14d8
#define MC_TXN_OVERRIDE_CONFIG_SCEW_0	0x14e0
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB_0	0x1318
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA_0	0x1300
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR_0	0x1310
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB_0	0x1338
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA_0	0x1320
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW_0	0x1330
#define MC_TXN_OVERRIDE_CONFIG_SESRD_0	0x1400
#define MC_TXN_OVERRIDE_CONFIG_SESWR_0	0x1408
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB_0	0x1430
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD_0	0x12a0
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB_0	0x1438
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR_0	0x12a8
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR_0	0x1480
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW_0	0x1488
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1_0	0x1510
#define MC_TXN_OVERRIDE_CONFIG_VICSRD_0	0x1360
#define MC_TXN_OVERRIDE_CONFIG_VICSWR_0	0x1368
#define MC_TXN_OVERRIDE_CONFIG_VIFALR_0	0x15e4
#define MC_TXN_OVERRIDE_CONFIG_VIFALW_0	0x15ec
#define MC_TXN_OVERRIDE_CONFIG_VIW_0	0x1390
#define MC_TXN_OVERRIDE_CONFIG_VIW_0_VIW_COH_PATH_OVERRIDE_NORMAL_FORCE_NON_COHERENT	1
#define MC_TXN_OVERRIDE_CONFIG_VIW_0_VIW_COH_PATH_OVERRIDE_NORMAL_RANGE	9:8
#define MC_TXN_OVERRIDE_CONFIG_VIW_0_VIW_COH_PATH_OVERRIDE_SO_DEV_FORCE_NON_COHERENT	1
#define MC_TXN_OVERRIDE_CONFIG_VIW_0_VIW_COH_PATH_OVERRIDE_SO_DEV_RANGE	5:4
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR_0	0x1260
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW_0	0x1268
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR_0	0x1250
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW_0	0x1258
#define MC_UFSHCPC2_PTSA_MAX_0	0x3a2c
#define MC_UFSHCPC2_PTSA_MAX_0_PTSA_MAX_UFSHCPC2_DEFAULT_MASK	0x7ff
#define MC_UFSHCPC2_PTSA_MIN_0	0x3a28
#define MC_UFSHCPC2_PTSA_MIN_0_PTSA_MIN_UFSHCPC2_DEFAULT_MASK	0x7ff
#define MC_UFSHCPC2_PTSA_RATE_0	0x3a24
#define MC_UFSHCPC2_PTSA_RATE_0_PTSA_RATE_UFSHCPC2_DEFAULT_MASK	0xfff
#define MC_UFSHCPC_PTSA_MAX_0	0x74c
#define MC_UFSHCPC_PTSA_MAX_0_PTSA_MAX_UFSHCPC_DEFAULT_MASK	0x7ff
#define MC_UFSHCPC_PTSA_MIN_0	0x748
#define MC_UFSHCPC_PTSA_MIN_0_PTSA_MIN_UFSHCPC_DEFAULT_MASK	0x7ff
#define MC_UFSHCPC_PTSA_RATE_0	0x744
#define MC_UFSHCPC_PTSA_RATE_0_PTSA_RATE_UFSHCPC_DEFAULT_MASK	0xfff
#define MC_USBD2_PTSA_MAX_0	0x3a44
#define MC_USBD2_PTSA_MAX_0_PTSA_MAX_USBD2_DEFAULT_MASK	0x7ff
#define MC_USBD2_PTSA_MIN_0	0x3a40
#define MC_USBD2_PTSA_MIN_0_PTSA_MIN_USBD2_DEFAULT_MASK	0x7ff
#define MC_USBD2_PTSA_RATE_0	0x3a3c
#define MC_USBD2_PTSA_RATE_0_PTSA_RATE_USBD2_DEFAULT_MASK	0xfff
#define MC_USBD_PTSA_MAX_0	0x538
#define MC_USBD_PTSA_MAX_0_PTSA_MAX_USBD_DEFAULT_MASK	0x7ff
#define MC_USBD_PTSA_MIN_0	0x534
#define MC_USBD_PTSA_MIN_0_PTSA_MIN_USBD_DEFAULT_MASK	0x7ff
#define MC_USBD_PTSA_RATE_0	0x530
#define MC_USBD_PTSA_RATE_0_PTSA_RATE_USBD_DEFAULT_MASK	0xfff
#define MC_USBX2_PTSA_MAX_0	0x3a38
#define MC_USBX2_PTSA_MAX_0_PTSA_MAX_USBX2_DEFAULT_MASK	0x7ff
#define MC_USBX2_PTSA_MIN_0	0x3a34
#define MC_USBX2_PTSA_MIN_0_PTSA_MIN_USBX2_DEFAULT_MASK	0x7ff
#define MC_USBX2_PTSA_RATE_0	0x3a30
#define MC_USBX2_PTSA_RATE_0_PTSA_RATE_USBX2_DEFAULT_MASK	0xfff
#define MC_USBX_PTSA_MAX_0	0x52c
#define MC_USBX_PTSA_MAX_0_PTSA_MAX_USBX_DEFAULT_MASK	0x7ff
#define MC_USBX_PTSA_MIN_0	0x528
#define MC_USBX_PTSA_MIN_0_PTSA_MIN_USBX_DEFAULT_MASK	0x7ff
#define MC_USBX_PTSA_RATE_0	0x524
#define MC_USBX_PTSA_RATE_0_PTSA_RATE_USBX_DEFAULT_MASK	0xfff
#define MC_VE_PTSA_MAX_0	0x43c
#define MC_VE_PTSA_MAX_0_PTSA_MAX_VE_DEFAULT_MASK	0x7ff
#define MC_VE_PTSA_MIN_0	0x438
#define MC_VE_PTSA_MIN_0_PTSA_MIN_VE_DEFAULT_MASK	0x7ff
#define MC_VE_PTSA_RATE_0	0x434
#define MC_VE_PTSA_RATE_0_PTSA_RATE_VE_DEFAULT_MASK	0xfff
#define MC_VICPC2_PTSA_MAX_0	0x3a14
#define MC_VICPC2_PTSA_MAX_0_PTSA_MAX_VICPC2_DEFAULT_MASK	0x7ff
#define MC_VICPC2_PTSA_MIN_0	0x3a10
#define MC_VICPC2_PTSA_MIN_0_PTSA_MIN_VICPC2_DEFAULT_MASK	0x7ff
#define MC_VICPC2_PTSA_RATE_0	0x3a0c
#define MC_VICPC2_PTSA_RATE_0_PTSA_RATE_VICPC2_DEFAULT_MASK	0xfff
#define MC_VICPC3_PTSA_MAX_0	0x7b8
#define MC_VICPC3_PTSA_MAX_0_PTSA_MAX_VICPC3_DEFAULT_MASK	0x7ff
#define MC_VICPC3_PTSA_MIN_0	0x7b4
#define MC_VICPC3_PTSA_MIN_0_PTSA_MIN_VICPC3_DEFAULT_MASK	0x7ff
#define MC_VICPC3_PTSA_RATE_0	0x7b0
#define MC_VICPC3_PTSA_RATE_0_PTSA_RATE_VICPC3_DEFAULT_MASK	0xfff
#define MC_VICPC_PTSA_MAX_0	0x55c
#define MC_VICPC_PTSA_MAX_0_PTSA_MAX_VICPC_DEFAULT_MASK	0x7ff
#define MC_VICPC_PTSA_MIN_0	0x558
#define MC_VICPC_PTSA_MIN_0_PTSA_MIN_VICPC_DEFAULT_MASK	0x7ff
#define MC_VICPC_PTSA_RATE_0	0x554
#define MC_VICPC_PTSA_RATE_0_PTSA_RATE_VICPC_DEFAULT_MASK	0xfff

#define EMC_FBIO_DATA_WIDTH	64
#define EMC_CFG_0	0xc
#define EMC_CFG_0_DRAM_ACPD_ACTIVE_POWERDOWN	1
#define EMC_CFG_0_DRAM_ACPD_NO_POWERDOWN	0
#define EMC_CFG_0_DRAM_ACPD_RANGE	29:29
#define EMC_CFG_0_DYN_SELF_REF_DISABLED	0
#define EMC_CFG_0_DYN_SELF_REF_ENABLED	1
#define EMC_CFG_0_DYN_SELF_REF_RANGE	28:28
#define EMC_TIMING_CONTROL_0	0x28
#define EMC_FBIO_CFG5_0	0x104
#define EMC_PMACRO_PAD_CFG_CTRL_0	0xc40

#define PCIE_COMMON_APPL_COMMON_CONTROL_0	0x0
#define PCIE_COMMON_APPL_COMMON_CONTROL_0_XBAR_CONFIG_RANGE	31:24

#define MSSNVLINK_MASTER_MCF_DDA_0	0x360
#define MSSNVLINK_MASTER_MCF_DDA_0_ENBL_DISABLE	0
#define MSSNVLINK_MASTER_MCF_DDA_0_ENBL_ENABLE	1
#define MSSNVLINK_MASTER_MCF_DDA_0_ENBL_RANGE	31:31
#define MSSNVLINK_MASTER_MCF_DDA_0_MAX_RANGE	26:16
#define MSSNVLINK_MASTER_MCF_DDA_0_RATE_RANGE	11:0

#define NV_MC_EMEM_NUM_SLOTS	63
#define NV_MC_EMEM_PTSA_RATE_WIDTH	12
#define NV_MC_EMEM_PTSA_MINMAX_WIDTH	10
#define EMC_FBIO_DATA_WIDTH 64
#define DISPLAY_CATCHUP_FACTOR 1.1f
#define MAX_NUM_DVFS_TIME_FREQS 104
#define NV_AFIR2MC_SR_REORDER_DEPTH	136
#define NV_AONDMAR2MC_SR_REORDER_DEPTH	32
#define NV_APEDMAR2MC_SR_REORDER_DEPTH	24
#define NV_AXISR2MC_SR_REORDER_DEPTH	32
#define NV_BPMPDMAR2MC_SR_REORDER_DEPTH	32
#define NV_EQOSR2MC_SR_REORDER_DEPTH	16
#define NV_GPUSRD2MC_SR_REORDER_DEPTH	256
#define NV_HOST1XDMAR2MC_SR_RDFIFODEPTH	32
#define NV_ISPRA2MC_SR_REORDER_DEPTH	128
#define NV_NVJPGSRD2MC_SR_RDFIFODEPTH	160
#define NV_SATAR2MC_SR_REORDER_DEPTH	16
#define NV_SCEDMAR2MC_SR_REORDER_DEPTH	32
#define NV_SDMMCR2MC_SR_REORDER_DEPTH	24
#define NV_SDMMCRA2MC_SR_REORDER_DEPTH	24
#define NV_SDMMCRAA2MC_SR_REORDER_DEPTH	48
#define NV_SDMMCRAB2MC_SR_REORDER_DEPTH	96
#define NV_SESRD2MC_SR_RDFIFODEPTH	136
#define NV_TSECSRD2MC_SR_RDFIFODEPTH	20
#define NV_TSECSRDB2MC_SR_RDFIFODEPTH	20
#define NV_UFSHCR2MC_SR_REORDER_DEPTH	72
#define NV_VICSRD2MC_SR_RDFIFODEPTH	225
#define NV_XUSB_DEVR2MC_SR_REORDER_DEPTH	40
#define NV_XUSB_HOSTR2MC_SR_REORDER_DEPTH	72

#endif
